1. Field of the Invention
This invention relates to an improved process for etching a via through an insulation layer to a lower metal layer. More particularly, this invention relates to an improved process for etching one or more vias through an insulation layer to a lower metal layer which inhibits deposition of residues containing sputtered metal, on the sidewalls of the via.
2. Description of the Related Art
Conventionally vias are etched through a dielectric layer, such as an oxide or nitride layer, to interconnect an upper metal layer with a lower metal layer beneath the insulation layer using plasma assisted etching systems with, for instance, CHF.sub.3 /O.sub.2, CHF.sub.3 /CF.sub.4, CHF.sub.3 /C.sub.2 F.sub.6, CHF.sub.3 /He, or CHF.sub.3 /Ar chemistries. However, such processes usually result in the deposition of etch residues or "backsputtered polymer" on the sidewall of one or more of the vias, which residues may include sputtered metal from the underlying metal layer.
Such backsputtered polymer etch residues may occur due to previous planarization of the oxide layer through which the vias are etched. Such planarization can result in some portions of the underlying metal layer (which is not planarized) being closer to the surface of the planarized insulation layer than other portions of the underlying metal. As a result, all of the vias will not be of the same depth and the underlying metal in a shallow via will be exposed while the insulation layer is still being etched to form the deeper vias. If the etchant system is not highly selective, some of the exposed underlying metal in the shallow via will be sputtered while the deeper vias are still being formed, resulting in the undesired backsputtered polymer etch residues being deposited on the walls of such shallow vias.
These residues are impossible to remove with a standard plasma photoresist strip etch. The sputtered metal deposited on the sidewalls of the vias is usually not pure metal, but rather a mixture of the metal and other etch residues. Such deposited material tends to clog the vias, preventing or inhibiting dry plasma stripping of the vias and thus tend to adversely influence subsequent filling of the vias with conducting material to electrically interconnect the lower metal layer with other portions of the integrated circuit structure, e.g., an upper metal layer or interconnect.
These metal-containing residues cannot be removed in standard plasma resist strip process steps and thus additional wet chemical treatment are typically necessary. Such additional process complexity and potential increased defect levels are not desirable.
It would, therefore, be advantageous to provide an etching process for the formation of vias through an insulation layer to an underlying metal layer which inhibits sputtering of the underlying metal and deposition of such sputtered metal and/or other etch residues on the sidewalls of the vias.